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Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random VT Variations on Timing.

B. Boroujeni, C. Piguet, and Y. Leblebici. PATMOS, volume 6448 of Lecture Notes in Computer Science, page 170-179. Springer, (2010)

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Yusuf

Erhan Leblebici

Nigem Yusuf

Faisal Yusuf

Sherif Yusuf

Other publications of authors with the same name

Weak inversion performance of CMOS and DCVSPG logic families in sub-300 mV range.O. Akgun, and Y. Leblebici. ISCAS, IEEE, (2006)Low-power current mode logic for improved DPA-resistance in embedded systems.Z. Deniz, and Y. Leblebici. ISCAS (2), page 1059-1062. IEEE, (2005)Sub-70 PS full adder IN 0.18 µm CMOS current-mode logic.E. Brauer, and Y. Leblebici. Circuits, Signals, and Systems, page 483-487. IASTED/ACTA Press, (2004)FIR filters for hardware-based real-time multi-band image blending.V. Popovic, and Y. Leblebici. Real-Time Image and Video Processing, volume 9400 of SPIE Proceedings, page 94000D. SPIE, (2015)3D configuration caching for 2D FPGAs.A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, P. Brisk, Y. Leblebici, P. Ienne, and M. Skerlj. FPGA, page 286. ACM, (2009)A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET.G. Kim, M. Kossel, A. Cevrero, I. Özkaya, A. Burg, T. Toifl, Y. Leblebici, L. Kull, D. Luu, M. Braendli and 5 other author(s). IEEE J. Solid State Circuits, 55 (1): 38-48 (2020)Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs.A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, A. Verma, S. Attarzadeh-Niaki, C. Nicopoulos, F. Gürkaynak, P. Brisk, Y. Leblebici, and P. Ienne. ACM Trans. Reconfigurable Technol. Syst., 2 (2): 13:1-13:36 (2009)Dynamically adaptive real-time disparity estimation hardware using iterative refinement.A. Akin, I. Baz, A. Schmid, and Y. Leblebici. Integr., 47 (3): 365-376 (2014)Nanowatt Range Folding-Interpolating Analog-to-Digital Converter Using Subthreshold Source-Coupled Circuits.A. Tajalli, and Y. Leblebici. J. Low Power Electron., 6 (1): 211-217 (2010)A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links.G. Kim, C. Cao, K. Gharibdoust, A. Tajalli, and Y. Leblebici. IEEE Trans. Circuits Syst. II Express Briefs, 64-II (12): 1387-1391 (2017)

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Disambiguation of "Leblebici, Yusuf"

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Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random VT Variations on Timing.

Please choose a person to relate this publication to

Yusuf

Erhan Leblebici

Nigem Yusuf

Faisal Yusuf

Sherif Yusuf

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Leblebici, Yusuf"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random VT Variations on Timing.

Please choose a person to relate this publication to

Yusuf

Erhan Leblebici

Nigem Yusuf

Faisal Yusuf

Sherif Yusuf

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random VT Variations on Timing.