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Disambiguation of "Dai, Fa Foster"

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An 802.11a/b/g/n Digital Fractional-N PLL With Automatic TDC Linearity Calibration for Spur Cancellation.

, , , , , and . IEEE J. Solid State Circuits, 52 (5): 1210-1220 (2017)

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Simon Foster

Esther Foster

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Paul Foster

 

Other publications of authors with the same name

A 3-dimensional Vernier ring time-to-digital converter in 0.13µm CMOS., and . CICC, page 1-4. IEEE, (2010)Multi-phase sub-sampling fractional-N PLL with soft loop switching for fast robust locking., , , and . CICC, page 1-4. IEEE, (2017)Session 24-Milimeter-wave communication circuits., and . CICC, page 1. IEEE, (2017)An 8-bit 80-MS/s Fully Self-Timed SAR ADC with 3/2 Interleaved Comparators and High-Order PVT Stabilized HBT Bandgap Reference., , , , and . ISCAS, page 1-4. IEEE, (2019)A 14-Bit, 1-ps resolution, two-step ring and 2D Vernier TDC in 130nm CMOS technology., and . ESSCIRC, page 143-146. IEEE, (2017)Selective Spectrum Analysis for Analog Measurements., , , , , and . IEEE Trans. Ind. Electron., 58 (10): 4960-4971 (2011)Effects of LO Phase and Amplitude Imbalances and Phase Noise on M -QAM Transceiver Performance., and . IEEE Trans. Ind. Electron., 57 (5): 1505-1517 (2010)A 6th order zero capacitor spread 1MHz - 10MHz tunable CMOS active-RC low pass filter with fast tuning scheme., and . ISCAS, page 1187-1190. IEEE, (2012)A 3mW 8-Bit radiation-hardened-by-design DAC for ultra-wide temperature range from -180°C to 120°C., and . ISCAS, page 997-1000. IEEE, (2011)A 7.7~10.3GHz 5.2mW -247.3dB-FOM Fractional-N Reference Sampling PLL with 2nd Order CDAC Based Fractional Spur Cancellation In 45nm CMOS., and . CICC, page 1-4. IEEE, (2020)