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A Novel Phase-Based Low Overhead Fault Tolerance Approach for VLIW Processors.

, , , , , and . ISVLSI, page 485-490. IEEE Computer Society, (2015)

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Generation and Propagation of Single Event Transients in CMOS Circuits., , , and . DDECS, page 198-203. IEEE Computer Society, (2006)Single event transients in combinatorial circuits., , , and . SBCCI, page 121-126. ACM, (2005)A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip., , , , , , , and . IEEE Trans. Computers, 57 (9): 1202-1215 (2008)Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies., , , , , and . VLSI-SoC, page 78-83. IEEE, (2007)A NOC closed-loop performance monitor and adapter., , , , , , and . Microprocess. Microsystems, 37 (6-7): 661-671 (2013)Accurate and computer efficient modelling of single event transients in CMOS circuits., , and . IET Circuits Devices Syst., 1 (2): 137-142 (2007)SET Fault Tolerant Combinational Circuits Based on Majority Logic., , , , and . DFT, page 345-352. IEEE Computer Society, (2006)Method to Analyze the Susceptibility of HLS Designs in SRAM-Based FPGAs Under Soft Errors., , , and . ARC, volume 9625 of Lecture Notes in Computer Science, page 132-143. Springer, (2016)Single event transients in dynamic logic., , , and . SBCCI, page 184-189. ACM, (2006)SET Susceptibility Analysis of Clock Tree and Clock Mesh Topologies., and . ISVLSI, page 559-564. IEEE Computer Society, (2014)