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Disambiguation of "Kulkarni, Jaydeep P."

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Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating.

, , , , , , , , and . IEEE J. Solid State Circuits, 52 (1): 50-63 (2017)

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Jaydeep Belapure

Jagadish Kulkarni

Praveen Kulkarni

Suchita Kulkarni

Aniket Kulkarni

 

Other publications of authors with the same name

4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging., , , , , , and . ISSCC, page 1-3. IEEE, (2015)Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (1): 2-13 (2010)A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array., , , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (9): 1727-1730 (2011)Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design., and . IEEE Trans. Very Large Scale Integr. Syst., 20 (2): 319-332 (2012)Thermal analysis of 8-T SRAM for nano-scaled technologies., , and . ISLPED, page 123-128. ACM, (2008)A GNN Computing-in-Memory Macro and Accelerator with Analog-Digital Hybrid Transformation and CAMenabled Search-reduce., , , , , , and . CICC, page 1-2. IEEE, (2023)Compute-in-eDRAM with Backend Integrated Indium Gallium Zinc Oxide Transistors., , and . ISCAS, page 1-5. IEEE, (2021)5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep., , , , , , , , , and 2 other author(s). ISSCC, page 108-109. IEEE, (2014)Aging Effects On Clock Gated Memory Phase Paths., , , and . DFT, page 1-5. IEEE, (2022)Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS., , , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)