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Disambiguation of "Nakajima, Masami"

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Design of Multiple-Valued Linear Digital Circuits for Highly Parallel k-Ary Operations.

, and . ISMVL, page 223-230. IEEE Computer Society, (1994)

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Yoshimichi Nakajima

Chikako Nakajima

Nanako Nakajima

Masaki Nakajima

Masami Th Nagatomo

 

Other publications of authors with the same name

Heterogeneous multicore SoC for secure multimedia applications., , , , , , , , , and 5 other author(s). CICC, page 675-678. IEEE, (2008)A 40GOPS 250mW massively parallel processor based on matrix architecture., , , , , , , , , and 2 other author(s). ISSCC, page 1616-1625. IEEE, (2006)A scalable massively parallel processor for real-time image processing., , , , , , , , , and 3 other author(s). ISSCC, page 334-335. IEEE, (2010)The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 42 (1): 183-192 (2007)Implementation and evaluation of FAST corner detection on the massively parallel embedded processor MX-G., , , , , and . CVPR Workshops, page 157-162. IEEE Computer Society, (2011)Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy., and . ISMVL, page 104-109. IEEE Computer Society, (1996)Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture., , and . IEICE Trans. Electron., 89-C (11): 1512-1518 (2006)Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 44 (8): 2251-2259 (2009)A Scalable Massively Parallel Processor for Real-Time Image Processing., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 46 (10): 2363-2373 (2011)Implementation of Face Recognition Processing Using an Embedded Processor., , , , , and . J. Robotics Mechatronics, 17 (4): 428-436 (2005)