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A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , and . VLSIC, page 12-. IEEE, (2015)

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