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A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products.

C. Jan, F. Al amoody, H. Chang, T. Chang, Y. Chen, N. Dias, W. Hafez, D. Ingerly, M. Jang, E. Karl, S. Shi, K. Komeyli, H. Kilambi, A. Kumar, K. Byon, C. Lee, J. Lee, T. Leo, P. Liu, N. Nidhi, R. Olac vaw, C. Petersburg, K. Phoa, C. Prasad, C. Quincy, R. Ramaswamy, T. Rana, L. Rockford, A. Subramaniam, C. Tsai, P. Vandervoorn, L. Yang, A. Zainuddin, and P. Bai. VLSIC, page 12-. IEEE, (2015)

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Aly M Hafez

Hafez Hafez

Hafez Mohamed Hafez

Kai Hafez

Hafez Shaheen

Other publications of authors with the same name

A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications.Y. Wang, H. Ahn, U. Bhattacharya, T. Coan, F. Hamzaoglu, W. Hafez, C. Jan, P. Kolar, S. Kulkarni, J. Lin and 6 other author(s). ISSCC, page 324-606. IEEE, (2007)Submicron Scaling of Indium Phosphide/indium Gallium Arsenide Heterojunction Bipolar Transistors Toward Terahertz BandwidthsW. Hafez. University of Illinois Urbana-Champaign, USA, (2005)E-Core Implementation in Intel 4 with PowerVia (Backside Power) Technology.M. Shamanna, E. Abuayob, G. Aenuganti, C. Alvares, J. Antony, A. Bahudhanam, A. Chandran, P. Chew, A. Chatterjee, B. Chauhan and 82 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products.C. Jan, F. Al amoody, H. Chang, T. Chang, Y. Chen, N. Dias, W. Hafez, D. Ingerly, M. Jang, E. Karl and 24 other author(s). VLSIC, page 12-. IEEE, (2015)A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications.Y. Wang, H. Ahn, U. Bhattacharya, Z. Chen, T. Coan, F. Hamzaoglu, W. Hafez, C. Jan, P. Kolar, S. Kulkarni and 7 other author(s). IEEE J. Solid State Circuits, 43 (1): 172-179 (2008)Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing.B. Sell, S. An, J. Armstrong, D. Bahr, B. Bains, R. Bambery, K. Bang, D. Basu, S. Bendapudi, D. Bergstrom and 73 other author(s). VLSI Technology and Circuits, page 282-283. IEEE, (2022)Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing.W. Hafez, P. Agnihotri, M. Asoro, M. Aykol, B. Bains, R. Bambery, M. Bapna, A. Barik, A. Chatterjee, P. Chiu and 52 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)

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Disambiguation of "Hafez, Walid M."