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Disambiguation of "Warnock, James D."

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CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications.

, , , , , , , , , , , , , and . IBM J. Res. Dev., 39 (1-2): 229-244 (1995)

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James D Edwards

James D Mueller

James D Mueller

David Warnock

Michael James

 

Other publications of authors with the same name

POWER7TM local clocking and clocked storage elements., , , , , , , and . ISSCC, page 178-179. IEEE, (2010)Cell Broadband Engine processor: Design and implementation., , and . IBM J. Res. Dev., 51 (5): 545-558 (2007)Design, CAD and technology challenges for future processors: 3D perspectives., , , , , and . DAC, page 212. ACM, (2011)Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module., , , , , , , , , and 15 other author(s). IEEE J. Solid State Circuits, 49 (1): 9-18 (2014)Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor., , , , , , , , , and 14 other author(s). IEEE J. Solid State Circuits, 41 (1): 179-196 (2006)Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 41 (8): 1692-1706 (2006)Design-synthesis co-optimisation using skewed and tapered gates., , , , , , and . DATE, page 1144-1147. IEEE, (2016)4.1 22nm Next-generation IBM System z microprocessor., , , , , , , , , and 21 other author(s). ISSCC, page 1-3. IEEE, (2015)Circuit and PD challenges at the 14nm technology node.. ISPD, page 66-67. ACM, (2013)IBM z13 circuit design and methodology., , , , , , , , , and 22 other author(s). IBM J. Res. Dev., (2015)