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Disambiguation of "Nakura, Toru"

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A Technique for Analyzing On-Chip Power Supply Impedance.

, , , , and . ATS, page 193-198. IEEE Computer Society, (2015)

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Toru Nomura

Toru Matsuyama

Toru Kashima

Richard Heinrich Torunsky

Ahmet Refah Torun

 

Other publications of authors with the same name

Fully automated PLL compiler generating final GDS from specification., and . ISQED, page 437-442. IEEE, (2016)A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion., , , and . VLSI-SoC, page 55-58. IEEE, (2018)One week TAT of 0.8μm CMOS gate array with analog elements for educational exercise., , , and . EWME, page 1-3. IEEE, (2016)All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter., , , , and . ASP-DAC, page 79-80. IEEE, (2011)All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter., , , , and . IEICE Trans. Electron., 94-C (4): 487-494 (2011)Cascaded Time Difference Amplifier with Differential Logic Delay Cell., , , , and . IEICE Trans. Electron., 94-C (4): 654-662 (2011)Autonomous di/dt Control of Power Supply for Margin Aware Operation., , and . IEICE Trans. Electron., 89-C (11): 1689-1694 (2006)Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply., , and . IEICE Trans. Electron., 89-C (3): 364-369 (2006)A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring., , , and . IEICE Trans. Electron., 100-C (9): 736-745 (2017)Spatial resolution improvement for point light source detection in scintillator cube using SPAD array with multi pinholes., , , , and . IEICE Electron. Express, 16 (19): 20190390 (2019)