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Adaptive Selection of Cache Indexing Bits for Removing Conflict Misses.

, , , , and . IEEE Trans. Computers, 64 (6): 1534-1547 (2015)

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Introduction to Part 2., , and . Trans. High Perform. Embed. Archit. Compil., (2007)Fence Placement for Legacy Data-Race-Free Programs via Synchronization Read Detection., , , and . ACM Trans. Archit. Code Optim., 12 (4): 46:1-46:23 (2016)A Generic Tool Supporting Cache Designs and Optimisation on Shared Memory Systems., , , and . PASA, volume P-124 of LNI, page 69-79. GI, (2008)Acceldroid: Co-designed acceleration of Android bytecode., , and . CGO, page 3:1-3:10. IEEE Computer Society, (2013)Phase-Based Application-Driven Hierarchical Power Management on the Single-chip Cloud Computer., , , and . PACT, page 131-142. IEEE Computer Society, (2011)ATOM: Atomic Durability in Non-volatile Memory through Hardware Logging., , , and . HPCA, page 361-372. IEEE Computer Society, (2017)DHTM: Durable Hardware Transactional Memory., , , and . ISCA, page 452-465. IEEE Computer Society, (2018)CAeSaR: Unified cluster-assignment scheduling and communication reuse for clustered VLIW processors., and . CASES, page 9:1-9:10. IEEE, (2013)Understanding the Effects of Data Corruption on Application Behavior Based on Data Characteristics., , and . SAFECOMP, volume 9337 of Lecture Notes in Computer Science, page 151-165. Springer, (2015)UCIFF: Unified Cluster Assignment Instruction Scheduling and Fast Frequency Selection for Heterogeneous Clustered VLIW Cores., and . LCPC, volume 7760 of Lecture Notes in Computer Science, page 127-142. Springer, (2012)