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Disambiguation of "Katashita, Toshihiro"

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Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates.

, , , , , , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (5): 827-840 (2012)

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Toshihiro Muramaki

Toshihiro Osada

 

Other publications of authors with the same name

Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function., , , and . ReConFig, page 223-228. IEEE Computer Society, (2011)Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device., , , and . IEICE Trans. Inf. Syst., 101-D (2): 303-313 (2018)A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (12): 2533-2541 (2013)Enhanced Correlation Power Analysis Using Key Screening Technique., , , , and . ReConFig, page 403-408. IEEE Computer Society, (2008)Prototype of USB stick-sized PUF module for authentication and key generation., , and . GCCE, page 1-2. IEEE, (2017)Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping., , , , , , and . Integr., (2020)Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption., , , , and . IEICE Trans. Inf. Syst., 96-D (11): 2333-2343 (2013)A Method of Generating Highly Efficient String Matching Circuit for Intrusion Detection., , , and . FPL, page 1-4. IEEE, (2006)Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays., , , , , and . J. Inf. Process., 22 (2): 344-356 (2014)A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation., , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (8): 1429-1438 (2015)