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Disambiguation of "Reddy, Karthikeyan"

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A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer.

, , , , , , and . IEEE J. Solid State Circuits, 47 (12): 2916-2927 (2012)

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Karthikeyan Balakrishnan

Karthikeyan Tangavelou

Karthikeyan Sharavanan

Edamakanti Chandrakanth Reddy

Karthikeyan Radhakrishnan

 

Other publications of authors with the same name

A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer., , , , , , and . ISSCC, page 152-154. IEEE, (2012)A VCO-based current-to-digital converter for sensor applications., , , , , , , and . CICC, page 1-4. IEEE, (2014)Fundamental Limitations of Continuous-Time Delta-Sigma Modulators Due to Clock Jitter., and . IEEE Trans. Circuits Syst. I Regul. Pap., 54-I (10): 2184-2194 (2007)A Highly Digital VCO-Based ADC Architecture for Current Sensing Applications., , , , , , , and . IEEE J. Solid State Circuits, 50 (8): 1785-1795 (2015)A 20.7mW continuous-time ΔΣ modulator with 15MHz bandwidth and 70 dB dynamic range., and . ESSCIRC, page 210-213. IEEE, (2008)Fundamental limitations of continuous-time delta-sigma modulators due to clock jitter., and . ISCAS, IEEE, (2006)A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer., , , , , , and . IEEE J. Solid State Circuits, 47 (12): 2916-2927 (2012)A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta-Sigma Modulator With VCO Quantizer Nonlinearity Cancellation., , , and . IEEE J. Solid State Circuits, 53 (3): 799-813 (2018)A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS., , , , , and . VLSIC, page 256-. IEEE, (2015)A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation., , , and . CICC, page 1-4. IEEE, (2017)