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Disambiguation of "Bhunia, Swarup"

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Nanomechanical non-volatile memory for computing at extreme.

, , , , , and . NANOARCH, page 44-45. IEEE Computer Society, (2013)

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Asamanjoy Bhunia

Anirban Bhunia

Krishna Swarup Jauhri

 

Other publications of authors with the same name

Self-Healing Design in Deep Scaled CMOS Technologies., , , , and . Journal of Circuits, Systems, and Computers, (2012)Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (6): 660-671 (2007)MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (6): 1005-1016 (2015)Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (9): 1034-1039 (2006)Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations., , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (11): 1286-1295 (2005)Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits, , and . CoRR, (2007)Internet of Things security: Are we paranoid enough?. ICCE, page 1. IEEE, (2018)Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies, , , , and . CoRR, (2007)ENFIRE: An Energy-efficient Fine-grained Spatio-temporal Reconfigurable Computing Fabric (Abstact Only)., , , and . FPGA, page 275. ACM, (2016)A study of asynchronous design methodology for robust CMOS-nano hybrid system design., and . JETC, 5 (3): 12:1-12:22 (2009)