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BiLink: A high performance NoC router architecture using bi-directional link with double data rate.

, , and . Integr., (2016)

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Finite state machine partitioning for low power., and . ISCAS (1), page 306-309. IEEE, (1999)Design and implementation of high-speed arbiter for large scale VOQ crossbar switches., , and . ISCAS (2), page 308-311. IEEE, (2003)A 10.6 pJ⋅K2 Resolution FoM Temperature Sensor Using Astable Multivibrator., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (7): 869-873 (2018)A thermal-aware application specific routing algorithm for Network-on-Chip design., and . ASP-DAC, page 449-454. IEEE, (2011)The Design of a Micro Power Management System for Applications Using Photovoltaic Cells With the Maximum Output Power Control., , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (8): 1138-1142 (2009)An Energy Efficient Layered Decoding Architecture for LDPC Decoder., and . IEEE Trans. Very Large Scale Integr. Syst., 18 (8): 1185-1195 (2010)Construction of Multi-Kernel Polar Codes With Kernel Substitution., , and . IEEE Wirel. Commun. Lett., 9 (11): 1879-1883 (2020)A Reconfigurable Winograd CNN Accelerator with Nesting Decomposition Algorithm for Computing Convolution with Large Filters., , and . CoRR, (2021)Low Power Rake Receiver and Viterbi Decoder Design for CDMA Applications., , and . Wireless Personal Communications, 14 (1): 49-64 (2000)Low Complexity SST Viterbi Decoder., and . VTC Fall, page 1-2. IEEE, (2006)