Author of the publication

Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study.

, , , and . DATE, page 228-233. IEEE Computer Society, (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study, , , and . CoRR, (2007)Hierarchical power supply noise evaluation for early power grid design prediction., , , and . SLIP, page 183-188. ACM, (2001)Error resilient JPEG2000 decoding for wireless applications., , , and . ICIP, page 2016-2019. IEEE, (2008)Optimized CORDIC core for frequency-domain motion estimation., , and . ICIP (3), page 1072-1075. IEEE, (2005)Implementation of a Flexible LDPC Decoder., , and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (6): 542-546 (2007)Look-ahead sphere decoding: algorithm and VLSI architecture., and . IET Commun., 5 (9): 1275-1285 (2011)A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods., and . DASIP, page 261-268. IEEE, (2011)Improving Network-on-Chip-based Turbo Decoder Architectures., and . J. Signal Process. Syst., 73 (1): 83-100 (2013)Coupled electro-thermal modeling and optimization of clock networks., , , , and . Microelectron. J., 34 (12): 1175-1185 (2003)An electromigration and thermal model of power wires for a priori high-level reliability prediction., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 12 (4): 349-358 (2004)