( en | de | ru )

 

Disambiguation of "Zografos, Odysseas"

Author of the publication

copydeleteadd this publication to your clipboard
Inversion optimization in Majority-Inverter Graphs.

, , , , , , , and . NANOARCH, page 15-20. ACM, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Odysseas Kontovourkis

Vasileios Zografos

Odysseas Papapetrou

Evangelos Zografos

 

Other publications of authors with the same name

Majority Logic Synthesis for Spin Wave Technology., , , , and . DSD, page 691-694. IEEE Computer Society, (2014)Area and routing efficiency of SWD circuits compared to advanced CMOS., , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era., , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (10): 1497-1506 (2022)A Novel System-Level Physics-Based Electromigration Modelling Framework: Application to the Power Delivery Network., , , , and . SLIP, page 1-7. IEEE, (2021)Overhead Reduction with Optimal Margining Using A Reliability Aware Design Paradigm., , , , , and . IRPS, page 1-7. IEEE, (2021)System-Level Simulation of Electromigration in a 3 nm CMOS Power Delivery Network: The Effect of Grid Redundancy, Metallization Stack and Standard-Cell Currents., , , , and . IRPS, page 1-7. IEEE, (2022)Majority logic synthesis., , , , , and . ICCAD, page 79. ACM, (2018)Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper)., , , , , , and . DATE, page 133-138. IEEE, (2020)Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper., , , , , , and . SLIP, page 3:1-3:5. ACM, (2022)Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs)., , , , , , , , , and 6 other author(s). IRPS, page 1-7. IEEE, (2023)