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Cross-Layer Optimization for Multilevel Cell STT-RAM Caches., , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (6): 1807-1820 (2017)基于多级磁自旋存储器的Cache调度策略的设计 (Design of Cache Scheduling Policies Based on MLC STT-RAM)., and . 计算机科学, 45 (6A): 513-517 (2018)Improving read performance of STT-MRAM based main memories through Smash Read and Flexible Read., , , and . ASP-DAC, page 31-36. IEEE, (2016)Unleashing the potential of MLC STT-RAM caches., , , and . ICCAD, page 429-436. IEEE, (2013)Balancing memory-accessing and computing over sparse DNN accelerator via efficient data packaging., , , , , , and . J. Syst. Archit., (2021)Hardware-Aware NAS Framework with Layer Adaptive Scheduling on Embedded System., , , , , , and . ASP-DAC, page 798-805. ACM, (2021)ExpoNAS: Using Exposure-based Candidate Exclusion to Reduce NAS Space for Heterogeneous Pipeline of CNNs., , , , and . ICPADS, page 1009-1014. IEEE, (2023)A smart protocol-level task mapping for energy efficient traffic on network-on-chip., and . Microprocess. Microsystems, (2019)An Energy-Efficient AES Encryption Algorithm Based on Memristor Switch., , , , and . ICA3PP (3), volume 12454 of Lecture Notes in Computer Science, page 639-653. Springer, (2020)TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations., , , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (10): 1985-1998 (2018)