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Disambiguation of "Shinohara, Hirofumi"

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Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits.

, , , , , and . CICC, page 1-4. IEEE, (2012)

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Kenichi Shinohara

Hirofumi Ishihara

Hirofumi Hosokawa

Hirofumi Kumazawa

Hirofumi Ueda

 

Other publications of authors with the same name

Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits., , , , , and . IEEE J. Solid State Circuits, 48 (8): 1986-1994 (2013)Design of a Sensorless Controller Synthesized by Robust H∞ Control for Boost Converters., , , and . IEICE Trans. Commun., 99-B (2): 356-363 (2016)Accurate Nanopower Supply-Insensitive CMOS Unit Vth Extractor and αVth Extractor with Continuous Variety., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 100-A (5): 1145-1155 (2017)Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature., , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (12): 918-921 (2012)60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations., , , , , and . ESSCIRC, page 317-320. IEEE, (2012)A BiCMOS wired-OR logic., , , , and . IEEE J. Solid State Circuits, 30 (6): 622-628 (June 1995)A 2.17-pJ/b 5b-Response Attack-Resistant Strong PUF with Enhanced Statistical Performance., , , , and . ESSCIRC, page 513-516. IEEE, (2022)A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture., , and . ICCD, page 202-205. IEEE Computer Society, (1993)A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology., , , , , , , , , and 15 other author(s). COOL Chips, page 1-3. IEEE Computer Society, (2014)A 64-bit carry look ahead adder using pass transistor BiCMOS gates., , , , and . IEEE J. Solid State Circuits, 31 (6): 810-818 (1996)