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FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration., , , , , , , , , and 6 other author(s). ESSDERC, page 110-113. IEEE, (2014)Fast Measurement of BTI on 28nm Fully Depleted Silicon-On-Insulator MOSFETs at Cryogenic Temperature down to 4K., , , , , , , , , and . IRPS, page 7. IEEE, (2022)19.2 A 110mK 295µW 28nm FDSOI CMOS Quantum Integrated Circuit with a 2.8GHz Excitation and nA Current Sensing of an On-Chip Double Quantum Dot., , , , , , , , , and 1 other author(s). ISSCC, page 306-308. IEEE, (2020)Recent advances in 3D VLSI integration., , , , , , , , , and 7 other author(s). ICICDT, page 1-4. IEEE, (2016)Design considerations for optimization of pull-in stability margin in electrostatic N/MEM relays., , , , , and . ICICDT, page 1-4. IEEE, (2017)3D monolithic integration., , , , , , , , , and 6 other author(s). ISCAS, page 2233-2236. IEEE, (2011)System on Wafer: A New Silicon Concept in SiP., , , , , , , , , and . Proc. IEEE, 97 (1): 60-69 (2009)Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors., , , , , and . ESSDERC, page 223-226. IEEE, (2021)Coupling control in the few-electron regime of quantum dot arrays using 2-metal gate levels in CMOS technology., , , , , , , , , and 6 other author(s). ESSCIRC, page 45-48. IEEE, (2022)Si MOS technology for spin-based quantum computing., , , , , , , , , and 7 other author(s). ESSDERC, page 12-17. IEEE, (2018)