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Power - Performance Optimization for Custom Digital Circuits., and . J. Low Power Electron., 2 (1): 113-120 (2006)Measurements and Analysis of Process Variability in 90nmCMOS., and . IEEE J. Solid State Circuits, 44 (5): 1655-1663 (2009)Energy-Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example., , and . IEEE J. Solid State Circuits, 44 (2): 569-583 (2009)A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band., , and . IEEE J. Solid State Circuits, 46 (11): 2524-2534 (2011)Power and Area Minimization for Multidimensional Signal Processing., , and . IEEE J. Solid State Circuits, 42 (4): 922-934 (2007)A generator of memory-based, runtime-reconfigurable 2N3M5K FFT engines., , and . ICASSP, page 1016-1020. IEEE, (2016)Managing variability for ultimate energy efficiency.. ECCTD, page 1-4. IEEE, (2011)Simpler, more efficient design.. ESSCIRC, page 20-25. IEEE, (2015)Level conversion for dual-supply systems., , and . IEEE Trans. Very Large Scale Integr. Syst., 12 (2): 185-195 (2004)A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI., , , , , , , , , and 1 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 28 (12): 2721-2725 (2020)