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Accelerating Graph and Machine Learning Workloads Using a Shared Memory Multicore Architecture with Auxiliary Support for In-hardware Explicit Messaging.

, , , , , and . IPDPS, page 254-264. IEEE Computer Society, (2017)

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MINIME-validator: Validating hardware with synthetic parallel testcases., , and . DATE, page 386-391. IEEE, (2017)MINIME: Pattern-Aware Multicore Benchmark Synthesizer., , , and . IEEE Trans. Computers, 64 (8): 2239-2252 (2015)Accelerating Synchronization Using Moving Compute to Data Model at 1, 000-core Multicore Scale., , , and . TACO, 16 (1): 4:1-4:27 (2019)Using software architectural patterns for synthetic embedded multicore benchmark development., , , and . IISWC, page 89-99. IEEE Computer Society, (2012)Functional Validation of a New Network Switch Architecture Using Rapid Prototyping Techniques., and . MTV, page 3-7. IEEE Computer Society, (2013)Stream synthesis for a wormhole run-time reconfigurable platform., and . FPL, volume 1304 of Lecture Notes in Computer Science, page 101-110. Springer, (1997)Retiming Verification Using Sequential Equivalence Checking., and . MTV, page 138-142. IEEE Computer Society, (2005)Accelerating Graph and Machine Learning Workloads Using a Shared Memory Multicore Architecture with Auxiliary Support for In-hardware Explicit Messaging., , , , , and . IPDPS, page 254-264. IEEE Computer Society, (2017)Efficient parallel packet processing using a shared memory many-core processor with hardware support to accelerate communication., , , and . NAS, page 122-129. IEEE Computer Society, (2015)Multicore Resource Isolation for Deterministic, Resilient and Secure Concurrent Execution of Safety-Critical Applications., , , and . IEEE Comput. Archit. Lett., 17 (2): 230-234 (2018)