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EIE: Efficient Inference Engine on Compressed Deep Neural Network.

, , , , , , and . ISCA, page 243-254. IEEE Computer Society, (2016)

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A tracking clock recovery receiver for 4-Gbps signaling., , and . IEEE Micro, 18 (1): 25-27 (1998)Express Cubes: Improving the Performance of k-Ary n-Cube Interconnection Networks.. IEEE Trans. Computers, 40 (9): 1016-1023 (1991)Deadlock-Free Message Routing in Multiprocessor Interconnection Networks., and . IEEE Trans. Computers, 36 (5): 547-553 (1987)Elastic Buffer Flow Control for On-Chip Networks., and . IEEE Trans. Computers, 62 (2): 295-309 (2013)Comparing Reyes and OpenGL on a Stream Architecture., , , and . Graphics Hardware, page 47-56. The Eurographics Association, (2002)The GPU Computing Era., and . IEEE Micro, 30 (2): 56-69 (2010)A Universal Parallel Computer Architecture.. New Generation Comput., 11 (3): 227-249 (1993)Invited.On-Demand Dynamic Branch Prediction., , , and . IEEE Comput. Archit. Lett., 14 (1): 50-53 (2015)SpArch: Efficient Architecture for Sparse Matrix Multiplication., , , and . HPCA, page 261-274. IEEE, (2020)DSD: Dense-Sparse-Dense Training for Deep Neural Networks., , , , , , , , , and 2 other author(s). ICLR (Poster), OpenReview.net, (2017)