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Threshold-voltage variability analysis and modeling for junctionless double-gate transistors.

C. Chen, J. Lin, and M. Chiang. Microelectron. Reliab., (2017)

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Meng Meng

Ching-Wen Hsueh

Yi-Ching Hsueh

Leo Fong-Ziang Hsueh

Chih-Jen Hsueh

Other publications of authors with the same name

Design issues and insights of multi-fin bulk silicon FinFETs.H. Li, and M. Chiang. ISQED, page 723-726. IEEE, (2012)MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization.W. Lin, H. Huang, K. Kao, M. Chiang, D. Lu, W. Hsu, Y. Wang, W. Ma, H. Tsai, Y. Lee and 3 other author(s). ESSDERC, page 9-12. IEEE, (2023)6-T SRAM performance assessment with stacked silicon nanowire MOSFETs.Y. Huang, M. Chiang, W. Hsu, and S. Cheng. ISQED, page 610-614. IEEE, (2015)Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications.Y. Huang, M. Chiang, and S. Wang. ISQED, page 231-234. IEEE, (2019)Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM.J. Chen, M. Chang, S. Chen, J. Lee, and M. Chiang. ISQED, page 151-155. IEEE, (2018)Assessment of structure variation in silicon nanowire FETs and impact on SRAM.Y. Liao, M. Chiang, K. Kim, and W. Hsu. Microelectron. J., 43 (5): 300-304 (2012)Low power design of phase-change memory based on a comprehensive model.M. Chiang, Y. Liao, J. Lin, W. Hsu, C. Yu, P. Chiang, Y. Hsu, W. Liu, S. Sheu, K. Su and 2 other author(s). IET Comput. Digit. Tech., 4 (4): 285-292 (2010)How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology.H. Chiang, R. Hadi, J. Wang, H. Han, J. Wu, H. Hsieh, J. Horng, W. Chou, B. Lien, C. Chang and 19 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Back-Bias Modulated UTBB SOI for System-on-Chip I/O Cells.M. Chang, P. Chao, and M. Chiang. ISQED, page 311. IEEE, (2021)An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires.Y. Huang, M. Chiang, S. Wang, and S. Gupta. ICICDT, page 117-120. IEEE, (2018)

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Disambiguation of "Chiang, Meng-Hsueh"

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Threshold-voltage variability analysis and modeling for junctionless double-gate transistors.

Please choose a person to relate this publication to

Meng Meng

Ching-Wen Hsueh

Yi-Ching Hsueh

Leo Fong-Ziang Hsueh

Chih-Jen Hsueh

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chiang, Meng-Hsueh"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Threshold-voltage variability analysis and modeling for junctionless double-gate transistors.

Please choose a person to relate this publication to

Meng Meng

Ching-Wen Hsueh

Yi-Ching Hsueh

Leo Fong-Ziang Hsueh

Chih-Jen Hsueh

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Threshold-voltage variability analysis and modeling for junctionless double-gate transistors.