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Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment., , , , and . DSD, page 634-640. IEEE Computer Society, (2007)An FPGA sliding window-based architecture harris corner detector., , and . FPL, page 1-4. IEEE, (2014)Layered LDPC decoder in-order message access scheduling: a case study., and . SACI, page 193-198. IEEE, (2020)Quantum circuit's reliability assessment with VHDL-based simulated fault injection., , , and . Microelectron. Reliab., 50 (2): 304-311 (2010)Performance Enhancement of Serial Based FPGA Probabilistic Fault Emulation Techniques., , and . DDECS, page 149-152. IEEE Computer Society, (2015)Memory-Centric Flooded LDPC Decoder Architecture Using Non-surjective Finite Alphabet Iterative Decoding., , and . DSD, page 104-109. IEEE Computer Society, (2018)Simulated Fault Injection for Quantum Circuits Based on Simulator Commands., , , , and . SACI, page 245-250. IEEE, (2007)Cost effective FPGA probabilistic fault emulation., , , and . NORCHIP, page 1-4. IEEE, (2014)SRT radix-2 dividers with (5, 4) redundant representation of partial remainder., and . NORCHIP, page 1-5. IEEE, (2013)Reliability analysis of memory centric LDPC decoders under probabilistic storage failures., , , and . ICECS, page 592-595. IEEE, (2016)