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Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs.

E. Beigné, A. Valentian, B. Giraud, O. Thomas, T. Benoist, Y. Thonnart, S. Bernard, G. Moritz, O. Billoint, Y. Maneglia, P. Flatresse, J. Noel, F. Abouzeid, B. Pelloux-Prayer, A. Grover, S. Clerc, P. Roche, J. Coz, S. Engels, and R. Wilson. DATE, page 613-618. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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An Asynchronous Power Aware and Adaptive NoC Based Circuit.E. Beigné, F. Clermidy, H. Lhermet, S. Miermont, Y. Thonnart, X. Tran, A. Valentian, D. Varreau, P. Vivet, X. Popon and 1 other author(s). IEEE J. Solid State Circuits, 44 (4): 1167-1177 (2009)3D NoC using through silicon Via: An asynchronous implementation.P. Vivet, D. Dutoit, Y. Thonnart, and F. Clermidy. VLSI-SoC, page 232-237. IEEE, (2011)Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology.B. Pelloux-Prayer, A. Valentian, B. Giraud, Y. Thonnart, J. Noel, P. Flatresse, and E. Beigné. VLSI-SoC, page 168-173. IEEE, (2013)SE2: Going Remote: Challenges and Opportunities to Remote Learning, Work, and Collaboration.A. Klinefelter, H. Liu, L. Benini, Y. Thonnart, K. Bowman, K. Wilcox, D. Bol, A. Loke, and O. Shacham. ISSCC, page 539-540. IEEE, (2021)A Cryogenic Active Router for Qubit Array Biasing from DC to 320 MHz at 100 nm Gate Pitch.B. Jadot, M. Zurita, G. Billiot, Y. Thonnart, L. Guevel, M. Darnas, C. Thomas, J. Charbonnier, T. Meunier, M. Vinet and 2 other author(s). ESSCIRC, page 157-160. IEEE, (2023)Complementary communication path for energy efficient on-chip optical interconnects.H. Li, S. Beux, Y. Thonnart, and I. O'Connor. DAC, page 7:1-7:6. ACM, (2015)Distributed Sequencing for Resource Sharing in Multi-applicative Heterogeneous NoC Platforms.Y. Thonnart, R. Lemaire, and F. Clermidy. NOCS, page 233-240. IEEE Computer Society, (2010)A Markov chain based method for NoC end-to-end latency evaluation.S. Foroutan, Y. Thonnart, R. Hersemeule, and A. Jerraya. IPDPS Workshops, page 1-8. IEEE, (2010)Introduction to the special session on "Silicon photonic interconnects: an illusion or a realistic solution?".J. Xu, S. Beux, and Y. Thonnart. NOCS, page 167. IEEE, (2014)Two-phase protocol converters for 3D asynchronous 1-of-n data links.J. Pontes, P. Vivet, and Y. Thonnart. ASP-DAC, page 154-159. IEEE, (2015)

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Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs.

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Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs.