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Disambiguation of "Richardson, Stephen"

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Improving energy efficiency of DRAM by exploiting half page row access.

, , , , and . MICRO, page 27:1-27:12. IEEE Computer Society, (2016)

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Dorothy Richardson

Kyle Richardson

Thomas Richardson

David Richardson

Susanne Richardson

 

Other publications of authors with the same name

An area-efficient minimum-time FFT schedule using single-ported memory., , , and . VLSI-SoC, page 39-44. IEEE, (2013)Bringing up a chip on the cheap., , , , , and . IEEE Des. Test, 29 (6): 57-65 (2012)Evaluating programmable architectures for imaging and vision applications., , , , , and . MICRO, page 52:1-52:13. IEEE Computer Society, (2016)Understanding sources of ineffciency in general-purpose chips., , , , , , , , and . Commun. ACM, 54 (10): 85-93 (2011)Code Optimization Across Procedures., and . Computer, 22 (2): 42-50 (1989)Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 59 (3): 947-959 (March 2024)Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains., , , , , , , , , and 1 other author(s). ACM Trans. Reconfigurable Technol. Syst., 16 (2): 26:1-26:28 (June 2023)Building Conflict-Free FFT Schedules., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (4): 1146-1155 (2015)Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra., , , , , , , , , and 13 other author(s). VLSI Technology and Circuits, page 70-71. IEEE, (2022)Intermediate representations for controllers in chip generators., , , , , and . DATE, page 1394-1399. IEEE, (2011)