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Interactive Outlining: An Improved Approach Using Active Contours.

, , , , , , and . Storage and Retrieval for Image and Video Databases (SPIE), volume 1908 of SPIE Proceedings, page 226-233. SPIE, (1993)

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Reasoning with Temporal Logic on Truncated Paths., , , , , and . CAV, volume 2725 of Lecture Notes in Computer Science, page 27-39. Springer, (2003)Functional design verification for microprocessors by error modeling.. University of Michigan, USA, (1999)High-Level Test Generation for Design Verification of Pipelined Microprocessors., , and . DAC, page 185-188. ACM Press, (1999)Timing verification of sequential dynamic circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (5): 645-658 (1999)The Definition of a Temporal Clock Operator., , , , and . ICALP, volume 2719 of Lecture Notes in Computer Science, page 857-870. Springer, (2003)Specification and verification of pipelining in the ARM2 RISC microprocessor., and . ACM Trans. Design Autom. Electr. Syst., 3 (4): 563-580 (1998)Collection and Analysis of Microprocessor Design Errors., , and . IEEE Des. Test Comput., 17 (4): 51-60 (2000)High-level design verification of microprocessors via error modeling., , , , and . ACM Trans. Design Autom. Electr. Syst., 3 (4): 581-599 (1998)Interactive Outlining: An Improved Approach Using Active Contours., , , , , , and . Storage and Retrieval for Image and Video Databases (SPIE), volume 1908 of SPIE Proceedings, page 226-233. SPIE, (1993)Timing verification of sequential domino circuits., , and . ICCAD, page 127-132. IEEE Computer Society / ACM, (1996)