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Disambiguation of "Hayashi, Terumine"

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Enhanced Delay Test Generator for High-Speed Logic LSIs.

, , , , , and . ITC, page 161-165. IEEE Computer Society, (1989)

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Ken Hayashi

Mutsumi Hayashi

Akiko Hayashi

Tetsuhiro Hayashi

Yoshiki Hayashi

 

Other publications of authors with the same name

Descriptive Answer Clustering System for Immediate Feedback., , , , and . ICCE, volume 162 of Frontiers in Artificial Intelligence and Applications, page 37-40. IOS Press, (2007)A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition., , , and . ASP-DAC, page 291-294. IEEE Computer Society, (1999)Manipulation of hidden units activities for fault tolerant multi-layer neural networks., , , and . CIRA, page 19-24. IEEE, (2003)LSI module placement methods using neural computation networks., , and . IJCNN, page 831-836. IEEE, (1990)Enhancing both generalization and fault tolerance of multilayer neural networks., , , and . IJCNN, page 1429-1433. IEEE, (2007)Low Power Oriented Test Modification and Compression Techniques for Scan Based Core Testing., , , , and . ATS, page 327-332. IEEE, (2006)Cyclic greedy generation method for limited number of IDDQ tests., , and . Asian Test Symposium, page 362-. IEEE Computer Society, (2000)Fault tolerant training algorithm for multi-layer neural networks focused on hidden unit activities., , and . IJCNN, page 1540-1545. IEEE, (2006)Shape of error surfaces in SpikeProp., , , and . IJCNN, page 840-844. IEEE, (2008)Sequential circuit test generation by real number simulation., , , and . Syst. Comput. Jpn., 24 (9): 64-75 (1993)