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Disambiguation of "Sim, Jae-Yoon"

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A Low-Power Class-AB Gm-Based Amplifier With Application to an 11-bit Pipelined ADC.

, , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (7): 2562-2569 (2016)

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Jae-Han Sim

Jae-Yoon Kim

Unyong Sim

Sim Hägele

Gavin Sim

 

Other publications of authors with the same name

5.5 A quadrature relaxation oscillator with a process-induced frequency-error compensation loop., , , , and . ISSCC, page 94-95. IEEE, (2017)A 490-pW SAR Temperature Sensor With a Leakage-Based Bandgap-Vth Reference., , and . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (9): 1549-1553 (2020)A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor., , , , , , , , and . IEEE J. Solid State Circuits, 38 (4): 631-640 (2003)Multipurpose Deep-Learning Accelerator for Arbitrary Quantization With Reduction of Storage, Logic, and Latency Waste., , , and . IEEE J. Solid State Circuits, 59 (1): 143-156 (January 2024)Analysis and prevention of DRAM latch-up during power-on., , , , , , , , and . IEEE J. Solid State Circuits, 32 (1): 79-85 (1997)A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme., , , , , and . IEEE J. Solid State Circuits, 37 (2): 245-250 (2002)A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines., , , , and . IEEE J. Solid State Circuits, 47 (9): 2068-2079 (2012)A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration., , , , , and . ISSCC, page 112-113. IEEE, (2008)An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface., , , , , , , and . ISSCC, page 136-138. IEEE, (2012)Low-Noise Distributed RC Oscillator., and . IEEE Trans. Very Large Scale Integr. Syst., 30 (2): 143-152 (2022)