( en | de | ru )

 

Disambiguation of "Kaliorakis, Manolis"

Author of the publication

copydeleteadd this publication to your clipboard
Cross-layer system reliability assessment framework for hardware faults.

, , , , , , , , , , , , , and . ITC, page 1-10. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Manolis Skarsoulis

Manolis Kamvysselis

Konstantin Manolis

Manolis Fanto

Manolis Pasparakis

 

Other publications of authors with the same name

Bayesian network early reliability evaluation analysis for both permanent and transient faults., , , , , , , and . IOLTS, page 7-12. IEEE, (2015)SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems., , , , , , , , , and 4 other author(s). IEEE Trans. Computers, 68 (5): 765-783 (2019)A Digital Twin for Maritime Situational Awareness., , , , , , , and . BDCAT, page 26:1-26:2. ACM, (2023)Statistical Analysis of Multicore CPUs Operation in Scaled Voltage Conditions., , , and . IEEE Comput. Archit. Lett., 17 (2): 109-112 (2018)A Scalable System for Maritime Route and Event Forecasting., , , , , , , , , and 2 other author(s). EDBT, page 762-769. OpenProceedings.org, (2024)Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs., , , , , , , , , and 2 other author(s). DSN Workshops, page 6-9. IEEE Computer Society, (2018)Microprocessor reliability-performance tradeoffs assessment at the microarchitecture level., , , , and . VTS, page 1-6. IEEE Computer Society, (2016)Micro-Viruses for Fast System-Level Voltage Margins Characterization in Multicore CPUs., , , , and . ISPASS, page 54-63. IEEE Computer Society, (2018)Cross-layer system reliability assessment framework for hardware faults., , , , , , , , , and 4 other author(s). ITC, page 1-10. IEEE, (2016)Versatile architecture-level fault injection framework for reliability evaluation: A first report., , , and . IOLTS, page 140-145. IEEE, (2014)