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Disambiguation of "Mathew, Sanu"

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A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS.

, , , , , , , , , and . A-SSCC, page 253-256. IEEE, (2016)

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Muhammad Sanusi

Rebecca Mathew

Stanley Mathew

Mathew Joseph

Mathew Mandapathil

 

Other publications of authors with the same name

Energy efficient and ultra low voltage security circuits for nanoscale CMOS technologies., , , and . CICC, page 1-4. IEEE, (2017)A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS., , , and . VLSI Design, page 301-306. IEEE Computer Society, (2009)Ultra-low energy circuit building blocks for security technologies., , , and . DATE, page 391-394. IEEE, (2018)A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array., , , , , , , , , and 2 other author(s). VLSI Circuits, page 238-. IEEE, (2019)A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures., , , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)μRNG: A 300-950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS., , , , , , , , , and 1 other author(s). ESSCIRC, page 116-119. IEEE, (2015)A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS., , , , , , , and . ESSCIRC, page 98-101. IEEE, (2018)Fine-Grained Electromagnetic Side-Channel Analysis Resilient Secure AES Core with Stacked Voltage Domains and Spatio-temporally Randomized Circuit Blocks., , , , , and . ESSCIRC, page 529-532. IEEE, (2022)Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators., , , , and . ARITH, page 84-87. IEEE, (2019)A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS., , , , , , , , and . CICC, page 1-4. IEEE, (2019)