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H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture.

, , , , , and . IET Comput. Digit. Tech., 9 (5): 259-267 (2015)

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Automatic Design Flow for Creating a Custom Multi-FPGA Board Netlist., , , and . ARC, volume 7806 of Lecture Notes in Computer Science, page 221. Springer, (2013)FPGA Interconnect Topologies Exploration., , , and . Int. J. Reconfigurable Comput., (2009)Efficient tree topology for FPGA interconnect network., , , and . ACM Great Lakes Symposium on VLSI, page 321-326. ACM, (2008)A multilevel hierarchical interconnection structure for FPGA., , , and . FPGA, page 225. ACM, (2006)Future inter-FPGA communication architecture for multi-FPGA based prototyping (abstract only)., , and . FPGA, page 251. ACM, (2014)Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA., , , and . ICECS, page 791-794. IEEE, (2009)Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA., , and . ReCoSoC, page 1-4. IEEE, (2011)ASIF: Application Specific Inflexible FPGA., , and . FPT, page 112-119. IEEE Computer Society, (2009)Estimation et optimisation de la consommation dans les SoC utilisant la simulation précise au cycle., , , , and . Technique et Science Informatiques, 27 (1-2): 203-233 (2008)Physical design exploration of 3D tree-based FPGA architecture., , , and . ACM Great Lakes Symposium on VLSI, page 335-336. ACM, (2013)