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The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack., , , , , , , , , and 14 other author(s). CoRR, (2023)Multilevel simulation-based co-design of next generation HPC microprocessors., , , , , , , , , and 10 other author(s). PMBS, page 18-29. IEEE, (2021)A firewall module resolving rules consistency., , and . WISES, page 47-50. IEEE, (2017)Soft real-time smartphone ECG processing., , , , , , and . SIES, page 1-4. IEEE, (2017)COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores., , , , , , , , , and 1 other author(s). ARCS, volume 13949 of Lecture Notes in Computer Science, page 105-119. Springer, (2023)Security in MPSoCs: A NoC Firewall and an Evaluation Framework., , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (8): 1344-1357 (2015)Security Enhancements for building saturation-free, low-power NoC-based MPSoCs., , , and . CNS, page 594-600. IEEE, (2015)Security Effectiveness and a Hardware Firewall for MPSoCs., , , , , , and . HPCC/CSS/ICESS, page 1032-1039. IEEE, (2014)Non-intrusive NoC DFS for Soft Real-Time Multimedia Applications., , , and . DSD, page 60-63. IEEE Computer Society, (2013)Address interleaving for low-cost NoCs., , , , and . ReCoSoC, page 1-8. IEEE, (2016)