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Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders.

, and . CoRR, (2016)

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A systematic methodology for design and analysis of approximate array multipliers., , , , and . APCCAS, page 352-354. IEEE, (2016)Synthesis of Semi-Classical Quantum Circuits., , and . J. Multiple Valued Log. Soft Comput., 18 (1): 99-114 (2012)Robust Quantum Algorithms Computing OR with epsilon-Biased Oracles., , , and . IEICE Trans. Inf. Syst., 90-D (2): 395-402 (2007)Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication., , , and . IEICE Trans. Inf. Syst., 96-D (1): 1-8 (2013)Multi-Party Quantum Communication Complexity with Routed Messages., , and . IEICE Trans. Inf. Syst., 92-D (2): 191-199 (2009)Changing the Gate Order for Optimal LNN Conversion., and . RC, volume 7165 of Lecture Notes in Computer Science, page 89-101. Springer, (2011)Quantum Sampling for Balanced Allocations., , and . COCOON, volume 2697 of Lecture Notes in Computer Science, page 304-318. Springer, (2003)Reducing the Overhead of Mapping Quantum Circuits to IBM Q System., , and . ISCAS, page 1-5. IEEE, (2019)A network-flow-based optimal sample preparation algorithm for digital microfluidic biochips., , and . ASP-DAC, page 225-230. IEEE, (2014)Reconfigurable 1-Bit Processor Array with Reduced Wirng Area., , , and . ERSA, page 225-234. CSREA Press, (2005)