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Disambiguation of "Morimoto, Makoto"

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A 1.4Mpixel CMOS image sensor with multiple row-rescan based data sampling for optical camera communication.

, , , , , , , and . A-SSCC, page 17-20. IEEE, (2014)

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Sei Morimoto

Makoto Yamamoto

Makoto Nakamura

Makoto Arai

Makoto Ida

 

Other publications of authors with the same name

A 187.5µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC., , , , , , , , , and 2 other author(s). ISSCC, page 494-495. IEEE, (2013)A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 57 (5): 1517-1526 (2022)A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems., , , , , , , , and . IEEE J. Solid State Circuits, 54 (4): 1086-1095 (2019)A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems., , , , , , , and . VLSI Circuits, page 149-150. IEEE, (2018)A 1.4Mpixel CMOS image sensor with multiple row-rescan based data sampling for optical camera communication., , , , , , , and . A-SSCC, page 17-20. IEEE, (2014)A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems., , , , , , , , , and 2 other author(s). ISSCC, page 478-480. IEEE, (2019)