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Enhancement of fault collection for embedded RAM redundancy analysis considering intersection and orphan faults., and . Integr., (2018)AI Architectures for Very Smart Sensors., and . Convergence of Artificial Intelligence and the Internet of Things, Springer, (2020)High Throughput Floating-Point Dividers Implemented in FPGA.. DDECS, page 291-294. IEEE Computer Society, (2015)MDCT IP Core Generator with Architectural Model Simulation., , , and . VLSI-SoC, page 18-23. IEEE, (2006)Natural logarithm and division floating-point high throughput co-processor implemented in FPGA.. NORCAS, page 1-6. IEEE, (2016)Machine Learning and Deep Learning frameworks and libraries for large-scale data mining: a survey., , , , , , , and . Artif. Intell. Rev., 52 (1): 77-124 (2019)Crop Mapping without Labels: Investigating Temporal and Spatial Transferability of Crop Classification Models Using a 5-Year Sentinel-2 Series and Machine Learning., , , , , , , and . Remote. Sens., 15 (13): 3414 (July 2023)FPGA Implementation of a Fast MDCT Algorithm., , , and . DDECS, page 228-229. IEEE Computer Society, (2006)High Throughput Floating Point Exponential Function Implemented in FPGA.. ISVLSI, page 97-100. IEEE Computer Society, (2015)A Generic IP Core of the Identical Forward and Inverse 12/36-Point MDCT Architecture and an Architectural Model Simulation Toolbox.. ICECS, page 709-712. IEEE, (2007)