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Automatic generation of loop scheduling for VLIW., , , and . PACT, page 306-309. IFIP Working Group on Algol / ACM, (1995)Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs., , , and . International Conference on Supercomputing, page 12-19. ACM, (1997)Runtime-assisted cache coherence deactivation in task parallel programs., , , , and . SC, page 35:1-35:12. IEEE / ACM, (2018)Memory Access Synchronization in Vector Multiprocessors., , and . CONPAR, volume 854 of Lecture Notes in Computer Science, page 414-425. Springer, (1994)Dynamic Cache Partitioning Based on the MLP of Cache Misses., , , and . Trans. High Perform. Embed. Archit. Compil., (2011)Errata on "Measuring Experimental Error in Microprocessor Simulation"., , , , , , and . SIGARCH Comput. Archit. News, 30 (1): 2-4 (2002)Partitioning: An Essential Step in Mapping Algorithms Into Systolic Array Processors., , and . Computer, 20 (7): 77-89 (1987)Register Constrained Modulo Scheduling., , , and . IEEE Trans. Parallel Distributed Syst., 15 (5): 417-430 (2004)Topic 15+20: Multimedia and Embedded Systems., , , and . Euro-Par, volume 2150 of Lecture Notes in Computer Science, page 651-652. Springer, (2001)Parallel Computer Architecture., , , and . Euro-Par, volume 1900 of Lecture Notes in Computer Science, page 537-538. Springer, (2000)