( en | de | ru )

 

Disambiguation of "Kimura, Shinji"

Author of the publication

copydeleteadd this publication to your clipboard
Hardware-oriented rate-distortion optimization algorithm for HEVC intra-frame encoder.

, , , and . ICME Workshops, page 1-6. IEEE Computer Society, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

T Kimura

Shuji Kimura

Shinji Koiwa

Shinji Maeda

Naoji Kimura

 

Other publications of authors with the same name

Foreword.. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (12): 2961 (2009)Multi-Operand Adder Synthesis Targeting FPGAs., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (12): 2579-2586 (2011)Issue Mechanism for Embedded Simultaneous Multithreading Processor., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (4): 1092-1100 (2008)Look Up Table Compaction Based on Folding of Logic Functions., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A (12): 2701-2707 (2002)Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (12): 3184-3191 (2003)A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor., , , , and . IEICE Trans. Electron., 100-C (3): 223-231 (2017)Sparseness Ratio Allocation and Neuron Re-pruning for Neural Networks Compression., , , and . ISCAS, page 1-5. IEEE, (2018)14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications., , , , , , , , , and 1 other author(s). ISSCC, page 266-268. IEEE, (2016)Framework for Parallel Prefix Adder Synthesis Considering Switching Activities., , and . IPSJ Trans. Syst. LSI Des. Methodol., (2009)Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (4): 996-1004 (2006)