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Systematic AUED Codes for Self-Checking Architectures., , and . DFT, page 183-191. IEEE Computer Society, (1998)Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study., , and . ICCD, page 131-. IEEE Computer Society, (1999)DeSpErate: Speeding-up design space exploration by using predictive simulation scheduling., , , and . DATE, page 1-4. European Design and Automation Association, (2014)MiCOMP: Mitigating the Compiler Phase-Ordering Problem Using Optimization Sub-Sequences and Machine Learning., , , , , and . TACO, 14 (3): 29:1-29:28 (2017)Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors., , , and . ICSAMOS, page 144-151. IEEE, (2006)A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems., , , , , and . SAC, page 672-678. ACM, (2003)Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques., , , and . ICSAMOS, page 118-124. IEEE, (2009)Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors., , , , , and . ACM Great Lakes Symposium on VLSI, page 440-443. ACM, (2004)A monitoring system for NoCs., , and . NoCArc@MICRO, page 25-30. ACM, (2010)Fast system-level exploration of memory architectures driven by energy-delay metrics., , , and . ISCAS (4), page 502-505. IEEE, (2001)