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Disambiguation of "Chrzanowska-Jeske, Malgorzata"

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Buffered Interconnects in 3D IC Layout Design.

, , and . SLIP, page 4:1-4:8. ACM, (2016)

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Malgorzata Ritter

Malgorzata Broncel

Malgorzata Sobiesiak

Malgorzata Kloczko

Malgorzata Liwinska

 

Other publications of authors with the same name

Regular symmetric arrays for non-symmetric functions.. ISCAS (1), page 391-394. IEEE, (1999)Substrate noise modeling in early floorplanning of MS-SOCs., , , and . ASP-DAC, page 819-823. ACM Press, (2005)Board-level multiterminal net assignment for the partial cross-bar architecture., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (3): 511-514 (2003)Modeling of substrate noise block properties for early prediction., and . ISCAS (3), page 3015-3018. IEEE, (2005)Generalized Inclusive Forms - New Canonical Reed-Muller Forms Including Minimum ESOPs., , and . VLSI Design, 14 (1): 13-21 (2002)Combining evolution strategies with Lagrangian relaxation for constructing nonslicing VLSI floorplans with soft modules., , and . IEEE Congress on Evolutionary Computation, page 1261-1266. IEEE, (2002)Buffered Interconnects in 3D IC Layout Design., , and . SLIP, page 4:1-4:8. ACM, (2016)ELF-SP - evolutionary algorithm for non-slicing floorplans with soft modules., , and . ICECS, page 681-684. IEEE, (2002)Generalized symmetric and generalized pseudo-symmetric functions.. ICECS, page 343-346. IEEE, (1999)Stochastic analysis of CNFET circuits using enhanced logical effort model in the presence of metallic tubes., , and . ICECS, page 774-777. IEEE, (2014)