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RASP 2.8: A new generation of floating-gate based field programmable analog array., , , , , , , and . CICC, page 213-216. IEEE, (2008)A Fully Integrated Architecture for Fast and Accurate Programming of Floating Gates Over Six Decades of Current., and . IEEE Trans. Very Large Scale Integr. Syst., 19 (6): 953-962 (2011)Robust doublet STDP in a floating-gate synapse., and . IJCNN, page 4296-4301. IEEE, (2014)Hardware and software infrastructure for a family of floating-gate based FPAAs., , , , , , , , and . ISCAS, page 2794-2797. IEEE, (2010)Domain Wall Motion-Based Dual-Threshold Activation Unit for Low-Power Classification of Non-Linearly Separable Functions., , , , and . IEEE Trans. Biomed. Circuits Syst., 12 (6): 1410-1421 (2018)Dynamics and Bifurcations in a Silicon Neuron., , and . IEEE Trans. Biomed. Circuits Syst., 4 (5): 320-328 (2010)A 0.11-0.38 pJ/cycle Differential Ring Oscillator in 65 nm CMOS for Robust Neurocomputing., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (2): 617-630 (2021)A 128-Channel Extreme Learning Machine-Based Neural Decoder for Brain Machine Interfaces., , and . IEEE Trans. Biomed. Circuits Syst., 10 (3): 679-692 (2016)Towards Intelligent Intracortical BMI (i2BMI): Low-Power Neuromorphic Decoders That Outperform Kalman Filters., , , , and . IEEE Trans. Biomed. Circuits Syst., 13 (6): 1615-1624 (2019)Hardware-Amenable Structural Learning for Spike-Based Pattern Classification Using a Simple Model of Active Dendrites., , and . Neural Comput., 27 (4): 845-897 (2015)