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Timing optimization of multiphase sequential logic.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (1): 51-62 (1991)

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Timing optimization of multiphase sequential logic., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (1): 51-62 (1991)SOCRATES: a system for automatically synthesizing and optimizing combinational logic., , , and . DAC, page 79-85. IEEE Computer Society Press, (1986)Multi-level logic minimization using implicit don't cares., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 7 (6): 723-740 (1988)Synthesis and Optimization of Multilevel Logic under Timing Constraints., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 5 (4): 582-596 (1986)