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Disambiguation of "Riener, Heinz"

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Designing reliable cyber-physical systems overview associated to the special session at FDL'16.

, , , , , , , , , , , , , , , , , , , and . FDL, page 1-8. IEEE, (2016)

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Cordian Riener

Robert Riener

Isabella Riener

Robert Riener

Robert Riener

 

Other publications of authors with the same name

Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development Cycle., , and . DATE, page 738-743. IEEE, (2020)Safety Synthesis Sans Specification., , , , and . CoRR, (2020)Three-Input Gates for Logic Synthesis., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (10): 2184-2188 (2021)Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits., , and . CoRR, (2021)Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis., , , and . ASP-DAC, page 395-402. IEEE, (2022)On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis., , , , and . DATE, page 1649-1654. IEEE, (2019)Evaluating ESOP Optimization Methods in Quantum Compilation Flows., , , , and . RC, volume 11497 of Lecture Notes in Computer Science, page 191-206. Springer, (2019)Design Understanding: From Logic to Specification*., , , , , and . VLSI-SoC, page 172-175. IEEE, (2018)Simulation-Guided Boolean Resubstitution., , , , and . CoRR, (2020)Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies., , , and . DATE, page 354-359. IEEE, (2021)