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Self-checking test circuits for latches and flip-flops.

, , , and . IOLTS, page 210-213. IEEE Computer Society, (2011)

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Constructive AIG optimization through functional composition., , and . ARCS Workshops, VDE-Verlag, (2011)CMOS inverter delay model based on DC transfer curve for slow input., , and . ISQED, page 651-657. IEEE, (2013)Advanced technology mapping for standard-cell generators., and . SBCCI, page 254-259. ACM, (2004)Exploring Independent Gates in FinFET-Based Transistor Network Generation., , , , and . SBCCI, page 41:1-41:6. ACM, (2014)Modeling and estimating leakage current in series-parallel CMOS networks., , , and . ACM Great Lakes Symposium on VLSI, page 269-274. ACM, (2007)Contributions to Modeling Patent Claims When Representing Patent Knowledge., , , and . AICOL, volume 10791 of Lecture Notes in Computer Science, page 140-156. Springer, (2017)Comparing Transistor-Level Implementations of 4-Input Logic Functions., , , and . IWLS, page 361-365. (2002)Optimization on cell-library design for digital Application Specific Printed Electronics Circuits., , , , and . PATMOS, page 1-6. IEEE, (2014)Improving the methodology to build non-series-parallel transistor arrangements., , , , , and . SBCCI, page 1-6. IEEE, (2013)Synthesis of threshold logic gates to nanoelectronics., , , and . SBCCI, page 1-6. IEEE, (2013)