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Coloring-based coalescing for graph coloring register allocation., , , , and . CGO, page 160-169. ACM, (2010)Quantitative comparison of hardware transactional memory for Blue Gene/Q, zEnterprise EC12, Intel Core, and POWER8., , , , and . ISCA, page 144-157. ACM, (2015)Reducing Rollbacks of Transactional Memory Using Ordered Shared Locks., , and . Euro-Par, volume 5704 of Lecture Notes in Computer Science, page 704-715. Springer, (2009)Profile-based Detection of Layered Bottlenecks., , , and . ICPE, page 197-208. ACM, (2019)A scheduling method for instruction-level parallel processing of vectorand scalar instructions., , , , and . Syst. Comput. Jpn., 30 (13): 23-33 (1999)Lock elision for read-only critical sections in Java., and . PLDI, page 269-278. ACM, (2010)Workload characterization for microservices., , and . IISWC, page 85-94. IEEE Computer Society, (2016)Compiler and Runtime Techniques for Software Transactional Memory Optimization, , , , , , , , , and 5 other author(s). Concurrency and Computation: Practice & Experience, 21 (1): 7--23 (2008)Transactional memory support in the IBM POWER8 processor., , , , , , , , and . IBM J. Res. Dev., (2015)Profile-based global live-range splitting., , , and . PLDI, page 216-227. ACM, (2006)