( en | de | ru )

 

Disambiguation of "Ritzenthaler, Romain"

Author of the publication

copydeleteadd this publication to your clipboard
Towards high performance sub-10nm finW bulk FinFET technology.

, , , , , , , , , , , , , , , , , , , and . ESSDERC, page 131-134. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Simone Ritzenthaler

Raphael Ritzenthaler

Bernhard Ritzenthaler

Romain Schroeder

Romain Brevet

 

Other publications of authors with the same name

Reliability impact of advanced doping techniques for DRAM peripheral MOSFETs., , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Thermally stable, packaged aware LV HKMG platforms benchmark to enable low power I/O for next 3D NAND generations., , , , , , , , , and 1 other author(s). IMW, page 1-4. IEEE, (2022)Isolation of nanowires made on bulk wafers by ground plane doping., , , , , and . ESSDERC, page 300-303. IEEE, (2017)Impact of Device Architecture and Gate Stack Processing on the Low-Frequency Noise of Silicon Nanowire Transistors., , , , , , , and . ASICON, page 1-4. IEEE, (2019)Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery., , , , , , , , , and 7 other author(s). IRPS, page 1-6. IEEE, (2022)PPAC scaling enablement for 5nm mobile SoC technology., , , , , , , , , and 7 other author(s). ESSDERC, page 240-243. IEEE, (2017)NBTI in Si0.55Ge0.45 cladding p-FinFETs: Porting the superior reliability from planar to 3D architectures., , , , , , , , , and . IRPS, page 2. IEEE, (2015)Impact of Off State Stress on advanced high-K metal gate NMOSFETs., , , , , , and . ESSDERC, page 365-368. IEEE, (2014)Reliability challenges in Forksheet Devices: (Invited Paper)., , , , , , , , , and 2 other author(s). IRPS, page 1-8. IEEE, (2023)Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices., , , , , , , , , and 6 other author(s). IRPS, page 1-8. IEEE, (2019)