Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R., , , , and . IEEE J. Solid State Circuits, 59 (3): 753-764 (March 2024)Bridging the P2P and WWW Divide with DISCOVIR - DIStributed COntent-based Visual Information Retrieval., , and . WWW (Posters), (2003)Split-SAR ADCs: Improved Linearity With Power and Speed Optimization., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (2): 372-383 (2014)A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (2): 557-568 (2021)A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (8): 1966-1976 (2017)9.6 A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial-Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration., , , and . ISSCC, page 164-166. IEEE, (2020)An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS., , , and . IEEE J. Solid State Circuits, 51 (5): 1223-1234 (2016)A 5.35-mW 10-MHz Single-Opamp Third-Order CT ΔΣ Modulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS., , , and . IEEE J. Solid State Circuits, 53 (10): 2783-2794 (2018)An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC., , , and . ESSCIRC, page 211-214. IEEE, (2014)A 0.46pJ/bit Ultralow-Power Entropy-Preselection-Based Strong PUF with Worst-Case BER-6., , , and . A-SSCC, page 1-3. IEEE, (2021)