( en | de | ru )

 

Disambiguation of "Martins, Rui Paulo"

Author of the publication

copydeleteadd this publication to your clipboard
Metastablility in SAR ADCs.

, , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (2): 111-115 (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Paulo Martins Engel

Paulo Ney Aguiar Martins

Milan Paulovic

Manuel António Paulo

Hartwig Paulo

 

Other publications of authors with the same name

Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques., , , , , , and . ASP-DAC, page 15-16. IEEE, (2016)Sub-µW QRS detection processor using quadratic spline wavelet transform and maxima modulus pair recognition for power-efficient wireless arrhythmia monitoring., , , and . ASP-DAC, page 21-22. IEEE, (2016)Frequency-downconversion and IF channel selection A-DQS sample-and-hold pair for two-step-channel-select low-IF receiver., , , and . ICECS, page 479-482. IEEE, (2003)A 0.22-to-2.4V-input fine-grained fully integrated rational buck-boost SC DC-DC converter using algorithmic voltage-feed-in (AVFI) topology achieving 84.1% peak efficiency at 13.2mW/mm2., , , and . ISSCC, page 422-424. IEEE, (2018)A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur., , , , and . ISSCC, page 270-272. IEEE, (2019)A 0.4 V 6.4 μW 3.3 MHz CMOS Bootstrapped Relaxation Oscillator with ±0.71% Frequency Deviation over -30 to 100 °C for Wearable and Sensing Applications., , and . ISCAS, page 1-5. IEEE, (2018)Experimental 1-V flexible-IF CMOS analoguebaseband chain for IEEE 802.11a/b/g WLAN receivers., , and . IET Circuits Devices Syst., 1 (6): 415-426 (2007)11.5 A 2-Phase Soft-Charging Hybrid Boost Converter with Doubled-Switching Pulse Width and Shared Bootstrap Capacitor Achieving 93.5% Efficiency at a Conversion Ratio of 4.5., , and . ISSCC, page 198-200. IEEE, (2020)Cost-Effective Compensation Design for Output Customization and Efficiency Optimization in Series/Series-Parallel Inductive Power Transfer Converter., , , , and . IEEE Trans. Ind. Electron., 67 (12): 10356-10365 (2020)A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations., , , , , , and . IEEE J. Solid State Circuits, 57 (3): 745-756 (2022)