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Design-space exploration of fault-tolerant building blocks for large-scale quantum computing.

, , , , and . NANOARCH, page 7-14. IEEE Computer Society, (2007)

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Design-space exploration of fault-tolerant building blocks for large-scale quantum computing., , , , and . NANOARCH, page 7-14. IEEE Computer Society, (2007)Characterization of Error-Tolerant Applications when Protecting Control Data., , , , , , and . IISWC, page 142-149. IEEE Computer Society, (2006)A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation., , and . MICRO, page 305-318. IEEE Computer Society, (2005)High-level interconnect model for the quantum logic array architecture., , , , and . ACM J. Emerg. Technol. Comput. Syst., 4 (1): 1:1-1:28 (2008)Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing., , , , and . ISCA, page 378-390. IEEE Computer Society, (2006)A Realizable Distributed Ion-Trap Quantum Computer., , and . HiPC, volume 4297 of Lecture Notes in Computer Science, page 111-122. Springer, (2006)Quantum Computing for Computer Architects, Second Edition, , and . Synthesis Lectures on Computer Architecture Morgan & Claypool Publishers, (2011)Quantum Computing for Computer Architects, and . Synthesis Lectures on Computer Architecture Morgan & Claypool Publishers, (2006)A pageable, defect-tolerant nanoscale memory system., , , and . NANOARCH, page 85-92. IEEE Computer Society, (2007)Combining static and dynamic defect-tolerance techniques for nanoscale memory systems., , , , and . ICCAD, page 773-778. IEEE Computer Society, (2007)