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CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors.

, , , , , , , and . DATE, page 707-712. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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CoRaS: A multiprocessor key corruption and random round swapping for power analysis side channel attacks: A DES case study., , and . ISCAS, page 253-256. IEEE, (2012)Improving GA-Based NoC Mapping Algorithms Using a Formal Model., , and . ISVLSI, page 344-349. IEEE Computer Society, (2014)MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm., , and . ICCAD, page 678-684. IEEE Computer Society, (2008)Composable local memory organisation for streaming applications on embedded MPSoCs., , , , , and . Conf. Computing Frontiers, page 23. ACM, (2011)Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks., , , and . IET Comput. Digit. Tech., 5 (1): 1-15 (2011)QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks., , , , and . ACM Trans. Design Autom. Electr. Syst., 26 (5): 33:1-33:36 (2021)DRMA: dynamically reconfigurable MPSoC architecture., , , , , , and . ACM Great Lakes Symposium on VLSI, page 239-244. ACM, (2013)A TDM NoC supporting QoS, multicast, and fast connection set-up., , , and . DATE, page 1283-1288. IEEE, (2012)Advanced modes in AES: Are they safe from power analysis based side channel attacks?, , , , and . ICCD, page 173-180. IEEE Computer Society, (2014)QuadSeal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks., , , , and . CASES, page 21-30. IEEE, (2015)